In various high density integrated circuit contexts, some components, such as analog or radiofrequency (“RF”) circuits are not located on a main die of the integrated circuit, sometimes designated a SOC main die. Typically, there are only high speed digital circuits on a SOC main die, such as standard cell, SRAM, digital PLL, and high speed memory input/output (“I/O”). Core devices are devices that are formed on such a die to provide high speed digital circuits, and generally operate faster, use lower voltages, have higher density, and are more susceptible to being overstressed and damaged.
I/O needs of a system typically deal with transferring signals between integrated circuit dies and component connections having large capacitances, such as those associated with printed circuit board traces, cables etc. that require larger driving power and voltage than the signaling occurring within the integrated circuit die. I/O devices interface the faster, smaller signals of a main die to these other, higher capacitance components, and typically transfer the signals at higher voltages.
The semiconductor standards body JEDEC provides at least two specifications pertaining to I/O for 3D IC applications, namely Wide I/O and Wide I/O 2, which are generally referred to herein collectively as Wide I/O. The Wide I/O specifications are directed to wide I/O applications having SDRAM (monolithic density) devices with thousands of wide I/O channels using direct chip-to-chip attachment methods between memory devices and a controller device. In Wide I/O, the power supply for data input/output buffers is specified at 1.2V±5%. Core devices on a typical main die, however, operate at a lower voltage, for example, 0.9 V and may be overstressed if operated at the I/O voltage level.
In various contexts, there is a need to provide a level shifter for the I/O demands of high density integrated circuits, such as those found in SOC and 3D IC applications.